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    Green Photonics and Electronics [[electronic resource] /] : монография / ed.: Eisenstein, Gadi., Bimberg, Dieter. - 1st ed. 2017. - [S. l. : s. n.]. - XIV, 291 p. 164 illus., 118 illus. in color. - Б. ц.
    Зміст:
Energy-efficient Vertical-cavity Surface-emitting Lasers for Optical Interconnects --
High-speed InP-based Long-wavelength VCSELs --
Quantum-Dot Semiconductor Optical Amplifiers for Energy-Efficient Optical Communication --
Quantum?Dot Mode?Locked Lasers: Sources for Tunable Optical and Electrical Pulse Combs --
Nanophotonic Approach to Energy-Ef?cient Ultra-Fast All-Optical Gates.
Рубрики: Renewable energy resources.
   Lasers.
   Photonics.
   Power electronics.
   Microprocessors.
   Energy systems.
   Renewable and Green Energy.
   Optics, Lasers, Photonics, Optical Devices.
   Power Electronics, Electrical Machines and Networks.
   Processor Architectures.
   Energy Systems.
Анотація: This books focuses on recent break-throughs in the development of a variety of photonic devices, serving distances ranging from mm to many km, together with their electronic counter-parts, e.g. the drivers for lasers, the amplifiers following the detectors and most important, the relevant advanced VLSI circuits. It explains that as a consequence of the increasing dominance of optical interconnects for high performance workstation clusters and supercomputers their complete design has to be revised. This book thus covers for the first time the whole variety of interdependent subjects contributing to green photonics and electronics, serving communication and energy harvesting. Alternative approaches to generate electric power using organic photovoltaic solar cells, inexpensive and again energy efficient in production are summarized. In 2015, the use of the internet consumed 5-6% of the raw electricity production in developed countries. Power consumption increases rapidly and without some transformational change will use, by the middle of the next decade at the latest, the entire electricity production. This apocalyptic outlook led to a redirection of the focus of data center and HPC developers from just increasing bit rates and capacities to energy efficiency. The high speed interconnects are all based on photonic devices. These must and can be energy efficient but they operate in an electronic environment and therefore have to be considered in a wide scope that also requires low energy electronic devices, sophisticated circuit designs and clever architectures. The development of the next generation of high performance exaFLOP computers suffers from the same problem: Their energy consumption based on present device generations is essentially prohibitive.

Перейти: https://doi.org/10.1007/978-3-319-67002-7

Дод.точки доступу:
Eisenstein, Gadi. \ed.\; Bimberg, Dieter. \ed.\; SpringerLink (Online service)
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    Parallel Architecture, Algorithm and Programming [[electronic resource] :] : 8th International Symposium, PAAP 2017, Haikou, China, June 17–18, 2017, Proceedings / / ed.: Chen, Guoliang., Shen, Hong., Chen, Mingrui. - 1st ed. 2017. - [S. l. : s. n.]. - XV, 629 p. 299 illus. - Б. ц.
Рубрики: Microprocessors.
   Numerical analysis.
   Data protection.
   Computer software.
   Computer engineering.
   Processor Architectures.
   Numeric Computing.
   Security.
   Professional Computing.
   Computer Engineering.
Анотація: This book constitutes the refereed proceedings of the 8th International Symposium on Parallel Architecture, Algorithm and Programming, PAAP 2017, held in Haikou, China, in June 2017. The 50 revised full papers and 7 revised short papers presented were carefully reviewed and selected from 192 submissions. The papers deal with research results and development activities in all aspects of parallel architectures, algorithms and programming techniques.

Перейти: https://doi.org/10.1007/978-981-10-6442-5

Дод.точки доступу:
Chen, Guoliang. \ed.\; Shen, Hong. \ed.\; Chen, Mingrui. \ed.\; SpringerLink (Online service)
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    Chen, Quan.
    Task Scheduling for Multi-core and Parallel Architectures [[electronic resource] :] : challenges, Solutions and Perspectives / / Quan. Chen, Guo, Minyi. ; . - 1st ed. 2017. - [S. l. : s. n.]. - XVIII, 243 p. 107 illus., 73 illus. in color. - Б. ц.
    Зміст:
Chapter 1 Introduction --
Chapter 2 Conventional Task Scheduling --
Chapter 3 Task Scheduling for Multi-socket Architecture --
Chapter 4 Task Scheduling for NUMA-enabled Architecture --
Chapter 5 Task Scheduling for Asymmetric Multi-core Architecture --
Chapter 6 Task Scheduling for Heterogeneous Parallel Architecture --
Chapter 7 Task Scheduling for Datacenter --
Chapter 8 Task Scheduling for Distributed System --
Chapter 9 Summary and Perspectives.
Рубрики: Microprocessors.
   Operating systems (Computers).
   Computer hardware.
   Computer science—Mathematics.
   Processor Architectures.
   Operating Systems.
   Computer Hardware.
   Mathematics of Computing.
Анотація: This book presents task-scheduling techniques for emerging complex parallel architectures including heterogeneous multi-core architectures, warehouse-scale datacenters, and distributed big data processing systems. The demand for high computational capacity has led to the growing popularity of multicore processors, which have become the mainstream in both the research and real-world settings. Yet to date, there is no book exploring the current task-scheduling techniques for the emerging complex parallel architectures. Addressing this gap, the book discusses state-of-the-art task-scheduling techniques that are optimized for different architectures, and which can be directly applied in real parallel systems. Further, the book provides an overview of the latest advances in task-scheduling policies in parallel architectures, and will help readers understand and overcome current and emerging issues in this field.

Перейти: https://doi.org/10.1007/978-981-10-6238-4

Дод.точки доступу:
Guo, Minyi.; Chen, Quan. \.\; SpringerLink (Online service)
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    VLSI Design and Test [[electronic resource] :] : 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers / / ed.: Kaushik, Brajesh Kumar., Dasgupta, Sudeb., Singh, Virendra. - 1st ed. 2017. - [S. l. : s. n.]. - XXI, 815 p. 486 illus. - Б. ц.
    Зміст:
Digital design --
Analog/mixed signal --
VLSI testing --
Devices and technology --
VLSI architectures --
Emerging technologies and memory --
System design --
Low power design and test --
RF circuits --
Architecture and CAD --
Design verification.
Рубрики: Computer hardware.
   Microprocessors.
   Computer communication systems.
   Computer Hardware.
   Processor Architectures.
   Computer Communication Networks.
Анотація: This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification.

Перейти: https://doi.org/10.1007/978-981-10-7470-7

Дод.точки доступу:
Kaushik, Brajesh Kumar. \ed.\; Dasgupta, Sudeb. \ed.\; Singh, Virendra. \ed.\; SpringerLink (Online service)
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    Advanced Parallel Processing Technologies [[electronic resource] :] : 12th International Symposium, APPT 2017, Santiago de Compostela, Spain, August 29, 2017, Proceedings / / ed. Dou, Yong. [et al.]. - 1st ed. 2017. - [S. l. : s. n.]. - IX, 129 p. 74 illus. - Б. ц.
    Зміст:
Platform-Adaptive High-Throughput Surveillance Video Condensation on Heterogeneous Processor Clusters --
Using Data Compression for Optimizing FPGA-based Convolutional Neural Network Accelerators --
Molecular docking Simulation Based on CPU-GPU Heterogeneous Computing --
FixCaffe: Training CNN with Low Precision Arithmetic Operations by Deep Learning Framework Caffe --
SysMon: Monitoring Memory Behaviors via OS Approach --
Self-adaptive Failure Detector for Peer-to-Peer Distributed System Considering the Link Faults --
A Survey about Quantitative Measurement of Performance Variability in High Performance Computers --
GDCRT: In-Memory 2D Geographical Dynamic Cascading Range Tree --
Eleven Code: A 3-Erasure MDS Code with Optimize Partial Stripes Writes --
Parallel Peer Pressure Clustering Algorithm based on Linear Algebra Computation --
T-List: A Concurrent Skip List Balanced on Search.
Рубрики: Software engineering.
   Algorithms.
   Computer communication systems.
   Operating systems (Computers).
   Programming languages (Electronic computers).
   Microprocessors.
   Software Engineering.
   Algorithm Analysis and Problem Complexity.
   Computer Communication Networks.
   Operating Systems.
   Programming Languages, Compilers, Interpreters.
   Processor Architectures.
Анотація: This book constitutes the proceedings of the 12th International Symposium on Advanced Parallel Processing Technologies, APPT 2017, held in Santiago de Compostela, Spain, in August 2017. The 11 regular papers presented in this volume were carefully reviewed and selected from 18 submissions. They deal with the recent advances in big data processing; parallel architectures and systems; parallel software; parallel algorithms and artificial intelligence applications; and distributed and cloud computing.

Перейти: https://doi.org/10.1007/978-3-319-67952-5

Дод.точки доступу:
Dou, Yong. \ed.\; Lin, Haixiang. \ed.\; Sun, Guangyu. \ed.\; Wu, Junjie. \ed.\; Heras, Dora. \ed.\; Bouge, Luc. \ed.\; SpringerLink (Online service)
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    Languages and Compilers for Parallel Computing [[electronic resource] :] : 29th International Workshop, LCPC 2016, Rochester, NY, USA, September 28-30, 2016, Revised Papers / / ed.: Ding, Chen., Criswell, John., Wu, Peng. - 1st ed. 2017. - [S. l. : s. n.]. - XI, 348 p. 137 illus. - Б. ц.
    Зміст:
Large Scale Parallelism --
Resilience and Persistence --
Compiler Analysis and Optimization --
Dynamic Computation and Languages --
GPUs and Private Memory --
Runt-time and Performance Analysis.
Рубрики: Programming languages (Electronic computers).
   Architecture, Computer.
   Computer programming.
   Software engineering.
   Operating systems (Computers).
   Microprocessors.
   Programming Languages, Compilers, Interpreters.
   Computer System Implementation.
   Programming Techniques.
   Software Engineering.
   Operating Systems.
   Processor Architectures.
Анотація: This book constitutes the thoroughly refereed post-conference proceedings of the 29th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2016, held in Rochester, NY, USA, in September 2016. The 20 revised full papers presented together with 4 short papers were carefully reviewed. The papers are organized in topical sections on large scale parallelism, resilience and persistence, compiler analysis and optimization, dynamic computation and languages, GPUs and private memory, and runt-time and performance analysis.

Перейти: https://doi.org/10.1007/978-3-319-52709-3

Дод.точки доступу:
Ding, Chen. \ed.\; Criswell, John. \ed.\; Wu, Peng. \ed.\; SpringerLink (Online service)
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    Transactions on Large-Scale Data- and Knowledge-Centered Systems XXXIV [[electronic resource] :] : special Issue on Consistency and Inconsistency in Data-Centric Applications / / ed. Hameurlain, Abdelkader. [et al.]. - 1st ed. 2017. - [S. l. : s. n.]. - IX, 185 p. 34 illus. - Б. ц.
    Зміст:
Basic Postulates for Inconsistency Measures --
Batch Composite Transactions in Stream Processing --
Enhancing User Rating Database Consistency through Pruning --
A Second Generation of Peer-to-Peer Semantic Wikis --
Formalizing a Paraconsistent Logic in the Isabelle Proof Assistant --
A Proximity-Based Understanding of Conditionals --
Inconsistency-Tolerant Database Repairs and Simplified Repair Checking by Measure-Based Integrity Checking.
Рубрики: Computer logic.
   Mathematical logic.
   Logic design.
   Operating systems (Computers).
   Microprocessors.
   Logics and Meanings of Programs.
   Mathematical Logic and Formal Languages.
   Logic Design.
   Operating Systems.
   Processor Architectures.
Анотація: LNCS journal Transactions on Large-Scale Data- and Knowledge-Centered Systems focuses on data management, knowledge discovery, and knowledge processing, which are core and hot topics in computer science. Since the 1990s, the Internet has become the main driving force behind application development in all domains. An increase in the demand for resource sharing across different sites connected through networks has led to an evolution of data- and knowledge-management systems from centralized systems to decentralized systems enabling large-scale distributed applications providing high scalability. Current decentralized systems still focus on data and knowledge as their main resource. Feasibility of these systems relies basically on P2P (peer-to-peer) techniques and the support of agent systems with scaling and decentralized control. Synergy between grids, P2P systems, and agent technologies is the key to data- and knowledge-centered systems in large-scale environments. This volume, the 34th issue of Transactions on Large-Scale Data- and Knowledge-Centered Systems, constitutes a special issue consisting of seven papers on the subject of Consistency and Inconsistency in Data-Centric Applications. The volume opens with an invited article on basic postulates for inconsistency measures. Three of the remaining six papers are revised, extended versions of papers presented at the First International Workshop on Consistency and Inconsistency, COIN 2016, held in conjunction with DEXA 2016 in Porto, Portugal, in September 2016. The other three papers were selected from submissions to a call for contributions to this edition. Each of the papers highlights a particular subtopic. However, all are concerned with logical inconsistencies that are either to be systematically avoided, or reasoned with consistently, i.e., without running the danger of an explosion of inferences.

Перейти: https://doi.org/10.1007/978-3-662-55947-5

Дод.точки доступу:
Hameurlain, Abdelkader. \ed.\; Kung, Josef. \ed.\; Wagner, Roland. \ed.\; Decker, Hendrik. \ed.\; SpringerLink (Online service)
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    Scaling OpenMP for Exascale Performance and Portability [[electronic resource] :] : 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20–22, 2017, Proceedings / / ed. de Supinski, Bronis R. [et al.]. - 1st ed. 2017. - [S. l. : s. n.]. - XI, 350 p. 116 illus. - Б. ц.
    Зміст:
Advanced Implementations and Extensions --
OpenMP Application Studies --
Analyzing and Extending Tasking --
OpenMP 4 Application Evaluation --
Extended Parallelism Models: Performance Analysis and Tools --
Advanced Data Management with OpenMP.
Рубрики: Microprocessors.
   Programming languages (Electronic computers).
   Special purpose computers.
   Logic design.
   Architecture, Computer.
   Computer programming.
   Processor Architectures.
   Programming Languages, Compilers, Interpreters.
   Special Purpose and Application-Based Systems.
   Logic Design.
   Computer System Implementation.
   Programming Techniques.
Анотація: This book constitutes the proceedings of the 13th International Workshop on OpenMP, IWOMP 2017, held in Stony Brook, NY, USA, in September 2017. The 23 full papers presented in this volume were carefully reviewed and selected from 28 submissions. They were organized in topical sections named: Advanced Implementations and Extensions; OpenMP Application Studies; Analyzing and Extending Tasking; OpenMP 4 Application Evaluation; Extended Parallelism Models: Performance Analysis and Tools; and Advanced Data Management with OpenMP.

Перейти: https://doi.org/10.1007/978-3-319-65578-9

Дод.точки доступу:
de Supinski, Bronis R. \ed.\; Olivier, Stephen L. \ed.\; Terboven, Christian. \ed.\; Chapman, Barbara M. \ed.\; Muller, Matthias S. \ed.\; SpringerLink (Online service)
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10.

    High Performance Computing [[electronic resource] :] : 32nd International Conference, ISC High Performance 2017, Frankfurt, Germany, June 18–22, 2017, Proceedings / / ed. Kunkel, Julian M. [et al.]. - 1st ed. 2017. - [S. l. : s. n.]. - XV, 432 p. 174 illus. - Б. ц.
    Зміст:
Applications and algorithms --
Proxy applications --
Architecture and system optimization --
Energy-aware computing.
Рубрики: Computer system failures.
   Computer software—Reusability.
   Microprocessors.
   Computers.
   Computer communication systems.
   System Performance and Evaluation.
   Performance and Reliability.
   Processor Architectures.
   Theory of Computation.
   Computer Communication Networks.
Анотація: This book constitutes the refereed proceedings of the 32nd International Conference, ISC High Performance 2017, held in Frankfurt, Germany, in June 2017. The 22 revised full papers presented in this book were carefully reviewed and selected from 66 submissions. The papers cover the following topics: applications and algorithms; proxy applications; architecture and system optimization; and energy-aware computing.

Перейти: https://doi.org/10.1007/978-3-319-58667-0

Дод.точки доступу:
Kunkel, Julian M. \ed.\; Yokota, Rio. \ed.\; Balaji, Pavan. \ed.\; Keyes, David. \ed.\; SpringerLink (Online service)
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11.

    Applications of Evolutionary Computation [[electronic resource] :] : 20th European Conference, EvoApplications 2017, Amsterdam, The Netherlands, April 19-21, 2017, Proceedings, Part I / / ed.: Squillero, Giovanni., Sim, Kevin. - 1st ed. 2017. - [S. l. : s. n.]. - XXIV, 905 p. 268 illus. - Б. ц.
    Зміст:
EvoBAFIN: Minimization of Systemic Risk for Directed Network Using Genetic Algorithm --
Pricing Rainfall Based Futures Using Genetic Programming --
Dynamic Portfolio Optimization in Ultra-High Frequency Environment --
EvoBIO: Integration of Reaction Kinetics Theory and Gene Expression Programming to Infer Reaction Mechanism --
De Novo DNA Assembly with a Genetic Algorithm Finds Accurate Genomes Even with Suboptimal Fitness --
EVE: Cloud-based Annotation of Human Genetic Variants --
Improving the Reproducibility of Genetic Association Results Using Genotype Resampling Methods --
Objective Assessment of Cognitive Impairment in Parkinson’s Disease Using Evolutionary Algorithm --
Characterizing the Influence of Rule-based Knowledge Representations in Biological Knowledge Extraction from Transcriptomics Data --
Enhancing Grammatical Evolution through Data Augmentation: Application to Blood Glucose Forecasting --
Genetic Programming Representations for Multi-dimensional Feature Learning in Biomedical Classification --
EvoCOMNET: Meta-heuristically Seeded Genetic Algorithm for Independent Job Scheduling in Grid Computing --
Analysis of Average Communicability in Complex Networks --
Configuring Dynamic Heterogeneous Wireless Communications Networks Using a Customized Genetic Algorithm --
Multi-Objective Evolutionary Algorithms for Influence Maximization in Social Networks --
A fast ILP-based Heuristic for the Robust Design of Body Wireless Sensor Networks --
EvoCOMPLEX: Lamarckian and Lifelong Memetic Search in Agent-based Computing --
Two-phase Strategy Managing Insensitivity in Global Optimization --
?Avenues for the Use of Cellular Automata in Image Segmentation --
Local Misfit Approximation in Memetic Solving of Ill-posed Inverse Problems --
The Two Regimes of Neutral Evolution: Localization on Hubs and Delocalized Diffusion --
EvoENERGY: Adaptive Batteries Exploiting On-line Steady-State Evolution Strategy --
Hybrid Multi-Ensemble Scheduling --
EvoGAMES: Driving in TORCS Using Modular Fuzzy Controllers --
Automated Game Balancing in Ms Pacman and StarCraft Using Evolutionary Algorithms --
Evolving Game-specific UCB Alternatives for General Video Game Playing --
Relief Camp Manager: A Serious Game Using the World Health Organization's Relief Camp Guidelines --
Analyisis of Vanilla Rolling Horizon Evolution Parameters in General Video Game Playing --
Darwin's Demons: Does Evolution Improve the Game --
EvoIASP: Evolutionary Art Using the Fly Algorithm --
Bagging and Feature Selection for Classification with Incomplete Data --
Surrogate-model Based Particle Swarm Optimization with Local Search for Feature Selection in Classification --
Feature Selection in High Dimensional Data by a Filter-Based Genetic Algorithm --
Brain Programming and the Random Search in Object Categorization --
Using Particle Swarm Optimization and the Silhouette Metric to Estimate the Number of Clusters, Select Features, and Perform Clustering --
EvoINDUSTRY: Container Vessel Stowage Planning System Using Genetic Algorithm --
The Artificial Immune Ecosystem: a Bio-inspired Meta-algorithm for Boosting Time Series Anomaly Detection with Expert Input --
Empirical Analysis of Optimization Methods for the Real-World Dial-a-Ride Problem --
EvoKNOW: Presenting the ECO: Evolutionary Computation Ontology --
A New Evolutionary Algorithm for Synchronization --
Large Scale Problems in Practice: The Effect of Dimensionality on the Interaction among Variables --
A Framework for Knowledge Integrated Evolutionary Algorithms --
DICE: A New Family of Bivariate Estimation of Distribution Algorithms Based on Dichotomized Multivariate Gaussian Distributions --
EvoNUM: Ranking Programming Languages for Evolutionary Algorithm Operations --
Distance-based Tournament Selection --
Preferences-Based Choice Prediction in Evolutionary Multi-Objective Optimization --
Numerical Optimization of ESA's Messenger Space Mission Benchmark --
EvoPAR: A VNS with Parallel Evaluation of Solutions for the Inverse Lighting Problem --
Evolving Cut-off Mechanisms and Other Work-Stealing Parameters for Parallel Programs --
Issues on GPU Parallel Implementation of Evolutionary High-dimensional Multi-objective Feature Selection --
Embedded Grammars for Grammatical Evolution on GPGPU --
A Performance Assessment of Evolutionary Algorithms in Volunteer Computing Environments: the Importance of Entropy --
EvoROBOT: Overcoming Initial Convergence in Multi-Objective Evolution of Robot Control and Morphology Using a Two-Phase Approach --
Evolutionary Adaptation to Social Information Use without Learning --
Interactive Evolution of Complex Behaviours through Skill Encapsulation --
Evolution and Morphogenesis of Simulated Modular Robots: A Comparison Between a Direct and Generative Encoding --
Continual and One-Shot Learning through Neural Networks with Dynamic External Memory.
Рубрики: Algorithms.
   Artificial intelligence.
   Special purpose computers.
   Architecture, Computer.
   Microprocessors.
   Logic design.
   Algorithm Analysis and Problem Complexity.
   Artificial Intelligence.
   Special Purpose and Application-Based Systems.
   Computer System Implementation.
   Processor Architectures.
   Logic Design.
Анотація: The two volumes LNCS 10199 and 10200 constitute the refereed conference proceedings of the 20th European Conference on the Applications of Evolutionary Computation, EvoApplications 2017, held in Amsterdam, The Netherlands, in April 2017, collocated with the Evo* 2016 events EuroGP, EvoCOP, and EvoMUSART. The 46 revised full papers presented together with 26 poster papers were carefully reviewed and selected from 108 submissions. EvoApplications 2016 consisted of the following 13 tracks: EvoBAFIN (natural computing methods in business analytics and finance), EvoBIO (evolutionary computation, machine learning and data mining in computational biology), EvoCOMNET (nature-inspired techniques for telecommunication networks and other parallel and distributed systems), EvoCOMPLEX (evolutionary algorithms and complex systems), EvoENERGY (evolutionary computation in energy applications), EvoGAMES (bio-inspired algorithms in games), EvoIASP (evolutionary computation in image analysis, signal processing, and pattern recognition), EvoINDUSTRY (nature-inspired techniques in industrial settings), EvoKNOW (knowledge incorporation in evolutionary computation), EvoNUM (bio-inspired algorithms for continuous parameter optimization), EvoPAR (parallel implementation of evolutionary algorithms), EvoROBOT (evolutionary robotics), EvoSET (nature-inspired algorithms in software engineering and testing), and EvoSTOC (evolutionary algorithms in stochastic and dynamic environments). .

Перейти: https://doi.org/10.1007/978-3-319-55849-3

Дод.точки доступу:
Squillero, Giovanni. \ed.\; Sim, Kevin. \ed.\; SpringerLink (Online service)
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12.

    Embedded Systems Design with Special Arithmetic and Number Systems [[electronic resource] /] : монография / ed.: Molahosseini, Amir Sabbagh., de Sousa, Leonel Seabra., Chang, Chip-Hong. - 1st ed. 2017. - [S. l. : s. n.]. - X, 389 p. 127 illus., 48 illus. in color. - Б. ц.
    Зміст:
Introduction to Residue Number System: Structure and Teaching Methodology --
RNS-based Embedded Processor Design --
Non Modular Operations of the Residue Number System: Functions for Computing --
Fault-Tolerant Computing in Redundant Residue Number System --
Decimal Floating Point Number System --
Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation --
Robust Analog Arithmetic Based on the Continuous Valued Number System --
RNS Applications in Digital Signal Processing --
RNS-based Image Processing --
Logarithmic Number System and its Application in FIR Filter Design --
Double-Base Number System and its Application in FIR Filter Design --
RNS-based Public-Key Cryptography (RSA and ECC) --
RNS Approach in Lattice-based Cryptography --
RNS Applications in Computer Networks.
Рубрики: Electronic circuits.
   Microprocessors.
   Electronics.
   Microelectronics.
   Circuits and Systems.
   Processor Architectures.
   Electronics and Microelectronics, Instrumentation.
Анотація: This book introduces readers to alternative approaches to designing efficient embedded systems using unconventional number systems. The authors describe various systems that can be used for designing efficient embedded and application-specific processors, such as Residue Number System, Logarithmic Number System, Redundant Binary Number System Double-Base Number System, Decimal Floating Point Number System and Continuous Valued Number System. Readers will learn the strategies and trade-offs of using unconventional number systems in application-specific processors and be able to apply and design appropriate arithmetic operations from these number systems to boost the performance of digital systems. • Serves as a single-source reference to designing embedded systems with unconventional number systems • Covers theory as well as implementation on application-specific processors • Explains mathematical concepts in a manner accessible to readers with diverse backgrounds.

Перейти: https://doi.org/10.1007/978-3-319-49742-6

Дод.точки доступу:
Molahosseini, Amir Sabbagh. \ed.\; de Sousa, Leonel Seabra. \ed.\; Chang, Chip-Hong. \ed.\; SpringerLink (Online service)
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13.

    Lourenco, Nuno.
    Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects [[electronic resource] /] : монография / Nuno. Lourenco, Martins, Ricardo., Horta, Nuno. ; . - 1st ed. 2017. - [S. l. : s. n.]. - XXVII, 182 p. 112 illus., 90 illus. in color. - Б. ц.
    Зміст:
Introduction --
Previous Works on Automatic Analog IC Sizing --
AIDA-C Architecture --
Multi-Objective Optimization Kernel --
AIDA-C Circuit Sizing Results --
Layout-Aware Circuit Sizing --
AIDA-C Layout-aware Circuit Sizing Results --
Conclusions.
Рубрики: Electronic circuits.
   Microprocessors.
   Electronics.
   Microelectronics.
   Circuits and Systems.
   Processor Architectures.
   Electronics and Microelectronics, Instrumentation.
Анотація: This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

Перейти: https://doi.org/10.1007/978-3-319-42037-0

Дод.точки доступу:
Martins, Ricardo.; Horta, Nuno.; Lourenco, Nuno. \.\; SpringerLink (Online service)
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14.

    Hardware IP Security and Trust [[electronic resource] /] : монография / ed.: Mishra, Prabhat., Bhunia, Swarup., Tehranipoor, Mark. - 1st ed. 2017. - [S. l. : s. n.]. - XII, 353 p. 131 illus., 78 illus. in color. - Б. ц.
    Зміст:
Part I. Introduction --
Chapter 1.Security and Trust Vulnerabilities in Third-party IPs --
PArt II.Trust Analysis --
Chapter 2.Security Rule Check --
Chapter 3.Digital Circuit Vulnerabilities to Hardware Trojans --
Chapter 4.Code Coverage Analysis for IP Trust Verification --
Chapter 5.Analyzing Circuit Layout to Probing Attack --
Chapter 6.Testing of Side Channel Leakage of Cryptographic IPs: Metrics and Evaluations --
Part III --
Effective Countermeasures --
Chapter 7.Hardware Hardening Approaches using Camouflaging, Encryption and Obfuscation --
Chapter 8.A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Passive Side Channel Attacks --
Part IV --
Chapter 9.Validation of IP Security and Trust --
Chapter 10.IP Trust Validation using Proof-carrying Hardware --
Chapter 11. Hardware Trust Verification --
Chapter 12.Verification of Unspecified IP Functionality --
Chapter 13.Verifying Security Properties in Modern SoCs using Instruction-level Abstractions --
Chapter 14. Test Generation for Detection of Malicious Parametric Variations --
Part V. Conclusions --
Chapter 15.The Future of Trustworthy SoC Design.
Рубрики: Electronic circuits.
   Data encryption (Computer science).
   Computer security.
   Electronics.
   Microelectronics.
   Microprocessors.
   Circuits and Systems.
   Cryptology.
   Systems and Data Security.
   Electronics and Microelectronics, Instrumentation.
   Processor Architectures.
Анотація: This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

Перейти: https://doi.org/10.1007/978-3-319-49025-0

Дод.точки доступу:
Mishra, Prabhat. \ed.\; Bhunia, Swarup. \ed.\; Tehranipoor, Mark. \ed.\; SpringerLink (Online service)
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15.

    Green IT Engineering: Concepts, Models, Complex Systems Architectures [[electronic resource] /] : монография / ed.: Kharchenko, Vyacheslav., Kondratenko, Yuriy., Kacprzyk, Janusz. - 1st ed. 2017. - [S. l. : s. n.]. - XIV, 305 p. 101 illus., 56 illus. in color. - Б. ц.
    Зміст:
Part I: Methodology and Principles of Green IT Engineering for Complex Systems --
Part II: Green Components and Programmable Systems --
Part III: Green Internet Computing, Cloud and Communication Systems --
Part IV: Modeling and Assessment of Green Computer Systems and Infrastructures --
Part V: Green PLC-Based Systems for Industry Applications.
Рубрики: Renewable energy resources.
   Microprocessors.
   Computational intelligence.
   Software engineering.
   Renewable and Green Energy.
   Processor Architectures.
   Computational Intelligence.
   Software Engineering.
   Renewable and Green Energy.
Анотація: This volume provides a comprehensive state of the art overview of a series of advanced trends and concepts that have recently been proposed in the area of green information technologies engineering as well as of design and development methodologies for models and complex systems architectures and their intelligent components. The contributions included in the volume have their roots in the authors’ presentations, and vivid discussions that have followed the presentations, at a series of workshop and seminars held within the international TEMPUS-project GreenCo project in United Kingdom, Italy, Portugal, Sweden and the Ukraine, during 2013-2015 and at the 1st - 5th Workshops on Green and Safe Computing (GreenSCom) held in Russia, Slovakia and the Ukraine. The book presents a systematic exposition of research on principles, models, components and complex systems and a description of industry- and society-oriented aspects of the green IT engineering. A chapter-oriented structure has been adopted for this book following a “vertical view” of the green IT, from hardware (CPU and FPGA) and software components to complex industrial systems. The 15 chapters of the book are grouped into five sections: (1) Methodology and Principles of Green IT Engineering for Complex Systems, (2) Green Components and Programmable Systems, (3) Green Internet Computing, Cloud and Communication Systems, (4) Modeling and Assessment of Green Computer Systems and Infrastructures, and (5) Green PLC-Based Systems for Industry Applications. The chapters provide an easy to follow, comprehensive introduction to the topics that are addressed, including the most relevant references, so that anyone interested in them can start the study by being able to easily find an introduction to the topic through these references. At the same time, all of them correspond to different aspects of the work in progress being carried out by various research groups throughout the world and, therefore, provide information on the state of the art of some of these topics, challenges and perspectives. .

Перейти: https://doi.org/10.1007/978-3-319-44162-7

Дод.точки доступу:
Kharchenko, Vyacheslav. \ed.\; Kondratenko, Yuriy. \ed.\; Kacprzyk, Janusz. \ed.\; SpringerLink (Online service)
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16.

    Deschamps, Jean-Pierre.
    Digital Systems [[electronic resource] :] : from Logic Gates to Processors / / Jean-Pierre. Deschamps, Valderrama, Elena., Teres, Lluis. ; . - 1st ed. 2017. - [S. l. : s. n.]. - XV, 241 p. 250 illus., 33 illus. in color. - Б. ц.
    Зміст:
Digital Systems --
Combinational circuits --
Arithmetic blocks --
Sequential circuits --
Synthesis of a processor --
Design methods --
Physical implementation -- .
Рубрики: Electronic circuits.
   Microprocessors.
   Electronics.
   Microelectronics.
   Circuits and Systems.
   Processor Architectures.
   Electronics and Microelectronics, Instrumentation.
Анотація: This textbook for a one-semester course in Digital Systems Design describes the basic methods used to develop “traditional” Digital Systems, based on the use of logic gates and flip flops, as well as more advanced techniques that enable the design of very large circuits, based on Hardware Description Languages and Synthesis tools. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn what a digital system is and how it can be developed, preparing them for steps toward other technical disciplines, such as Computer Architecture, Robotics, Bionics, Avionics and others. In particular, students will learn to design digital systems of medium complexity, describe digital systems using high level hardware description languages, and understand the operation of computers at their most basic level. All concepts introduced are reinforced by plentiful illustrations, examples, exercises, and applications. For example, as an applied example of the design techniques presented, the authors demonstrate the synthesis of a simple processor, leaving the student in a position to enter the world of Computer Architecture and Embedded Systems. Provides textbook coverage for one-semester, introductory course in Digital Systems; Explains how to develop digital systems, starting from a functional specification; Emphasizes the relationship between algorithms and circuits (top down approach) and on the use of high level languages (Pseudo-code, VHDL, C); Describes the main problems development engineers are faced with, during the process of developing a new circuit; Demonstrates which design tools are necessary to develop a new circuit; Includes numerous, solved-examples in-text, as well as end of chapter exercises.

Перейти: https://doi.org/10.1007/978-3-319-41198-9

Дод.точки доступу:
Valderrama, Elena.; Teres, Lluis.; Deschamps, Jean-Pierre. \.\; SpringerLink (Online service)
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17.

    Martins, Ricardo.
    Analog Integrated Circuit Design Automation [[electronic resource] :] : placement, Routing and Parasitic Extraction Techniques / / Ricardo. Martins, Lourenco, Nuno., Horta, Nuno. ; . - 1st ed. 2017. - [S. l. : s. n.]. - XVI, 207 p. 108 illus., 79 illus. in color. - Б. ц.
    Зміст:
1 Introduction --
2 State-of-the-Art on Analog Layout Automation --
3 AIDA-L: Architecture and Integration --
4 Template-based Placer --
5 Optimization-based Placer --
6 Fully-Automatic Router --
7 Empirical-based Parasitic Extractor --
8 Experimental Results --
9 Conclusions and Future Work.
Рубрики: Electronic circuits.
   Microprocessors.
   Electronics.
   Microelectronics.
   Circuits and Systems.
   Processor Architectures.
   Electronics and Microelectronics, Instrumentation.
Анотація: This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.

Перейти: https://doi.org/10.1007/978-3-319-34060-9

Дод.точки доступу:
Lourenco, Nuno.; Horta, Nuno.; Martins, Ricardo. \.\; SpringerLink (Online service)
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18.

    Carbon Nanotubes for Interconnects [[electronic resource] :] : process, Design and Applications / / ed.: Todri-Sanial, Aida., Dijon, Jean., Maffucci, Antonio. - 1st ed. 2017. - [S. l. : s. n.]. - XII, 333 p. 167 illus., 133 illus. in color. - Б. ц.
    Зміст:
Interconnect challenges for 2D and 3D Integration --
Overview of Carbon Nanotube Physical Properties --
Overview of Carbon Nanotube Processing Methods --
Electrical Conductivity of Carbon Nanotubes – Modeling and Characterization --
Computational Studies of Thermal Transport Properties of Carbon Nanotube Material --
Overview of Carbon Nanotubes for Horizontal On-Chip Interconnects --
Carbon Nanotubes as Vertical Interconnects for 3D ICs --
Carbon Nanotubes as Micro-Bumps for 3D Integration --
Electrothermal Modeling of Carbon Nanotubes TSVs --
Exploring Carbon Nanotubes for 3D Power Delivery Networks --
Carbon Nanotubes for Monolithic 3D ICs.
Рубрики: Electronic circuits.
   Microprocessors.
   Circuits and Systems.
   Processor Architectures.
   Electronic Circuits and Devices.
Анотація: This book provides a single-source reference on the use of carbon nanotubes (CNTs) as interconnect material for horizontal, on-chip and 3D interconnects. The authors demonstrate the uses of bundles of CNTs, as innovative conducting material to fabricate interconnect through-silicon vias (TSVs), in order to improve the performance, reliability and integration of 3D integrated circuits (ICs). This book will be first to provide a coherent overview of exploiting carbon nanotubes for 3D interconnects covering aspects from processing, modeling, simulation, characterization and applications. Coverage also includes a thorough presentation of the application of CNTs as horizontal on-chip interconnects which can potentially revolutionize the nanoelectronics industry. This book is a must-read for anyone interested in the state-of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits. Provides a single-source reference on carbon nanotubes for interconnect applications; Includes complete coverage of current Cu-based interconnect problems for both 2D and 3D interconnects; Covers topics from modeling, simulation, analysis, design and characterization, in order to provide a broad view of the application of carbon nanotubes for interconnects.

Перейти: https://doi.org/10.1007/978-3-319-29746-0

Дод.точки доступу:
Todri-Sanial, Aida. \ed.\; Dijon, Jean. \ed.\; Maffucci, Antonio. \ed.\; SpringerLink (Online service)
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19.

    Emerging Technology and Architecture for Big-data Analytics [[electronic resource] /] : монография / ed.: Chattopadhyay, Anupam., Chang, Chip Hong., Yu, Hao. - 1st ed. 2017. - [S. l. : s. n.]. - XI, 330 p. 162 illus., 98 illus. in color. - Б. ц.
    Зміст:
Part I State-of-the-Art Architectures and Automation for Data-analytics --
Chapter 1. Scaling the Java Virtual Machine on a Many-core System --
Chapter 2.Scaling the Java Virtual Machine on a Many-core System --
Chapter 3.Least-squares based Machine Learning Accelerator for Big-data Analytics in Smart Buildings --
Chapter 4.Compute-in-memory Architecture for Data-Intensive Kernels --
Chapter 5. New Solutions for Cross-Layer System-Level and High-Level Synthesis --
Part II New Solutions for Cross-Layer System-Level and High-Level Synthesis --
Chapter 6.Side Channel Attacks and Efficient Countermeasures on Residue Number System Multipliers --
Chapter 7. Ultra-Low-Power Biomedical Circuit Design and Optimization: Catching The Don’t Cares --
Chapter 8.Acceleration of MapReduce Framework on a Multicore Processor --
Chapter 9. Adaptive dynamic range compression for improving envelope-based speech perception: Implications for cochlear implants --
Part III Emerging Technology, Circuits and Systems for Data-analytics --
Chapter 10. Emerging Technology, Circuits and Systems for Data-analytics --
Chapter 11. Energy Efficient Spiking Neural Network Design with RRAM Devices --
Chapter 12. Efficient Neuromorphic Systems and Emerging Technologies - Prospects and Perspectives --
Chapter 13. In-memory Data Compression Using ReRAMs --
Chapter 14. In-memory Data Compression Using ReRAMs --
Chapter 15.Data Analytics in Quantum Paradigm – An Introduction.
Рубрики: Electronic circuits.
   Microprocessors.
   Big data.
   Circuits and Systems.
   Processor Architectures.
   Electronic Circuits and Devices.
   Big Data/Analytics.
Анотація: This book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes emerging technology and devices for data-analytics, circuit design for data-analytics, and architecture and algorithms to support data-analytics. Readers will benefit from the realistic context used by the authors, which demonstrates what works, what doesn’t work, and what are the fundamental problems, solutions, upcoming challenges and opportunities. Provides a single-source reference to hardware architectures for big-data analytics; Covers various levels of big-data analytics hardware design abstraction and flow, from device, to circuits and systems; Demonstrates how non-volatile memory (NVM) based hardware platforms can be a viable solution to existing challenges in hardware architecture for big-data analytics.

Перейти: https://doi.org/10.1007/978-3-319-54840-1

Дод.точки доступу:
Chattopadhyay, Anupam. \ed.\; Chang, Chip Hong. \ed.\; Yu, Hao. \ed.\; SpringerLink (Online service)
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20.

    Hardware Security and Trust [[electronic resource] :] : design and Deployment of Integrated Circuits in a Threatened Environment / / ed. Sklavos, Nicolas. [et al.]. - 1st ed. 2017. - [S. l. : s. n.]. - X, 254 p. 99 illus., 47 illus. in color. - Б. ц.
    Зміст:
AES Datapaths on FPGAs: a State of the Art Analysis --
Fault Attacks, Injection Techniques and Tools for Simulation --
Recent developments in side-channel analysis on Elliptic Curve Cryptography implementations --
Practical Session: Differential Power Analysis for Beginners --
Fault and Power Analysis Attack Protection Techniques for Standardized Public Key Cryptosystems --
Scan Design: Basics, Advancements and Vulnerabilities --
Manufacturing Testing & Security Countermeasures --
Malware Threats and Solutions for Trustworthy Mobile Systems Design --
Ring Oscillators and Hardware Trojan Detection --
Notions on Silicon Physically Unclonable Functions --
Implementation of delay-based PUFs on Altera FPGAs --
Implementation and Analysis of Ring Oscillator Circuits on Xilinx FPGAs.-.
Рубрики: Electronic circuits.
   Microprocessors.
   Electronics.
   Microelectronics.
   Circuits and Systems.
   Processor Architectures.
   Electronics and Microelectronics, Instrumentation.
Анотація: This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers. Covers all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization; Describes new methods and algorithms for the identification/detection of hardware trojans; Defines new architectures capable of detecting faults and resisting fault attacks; Establishes a design and synthesis flow to transform a given circuit into a secure design, incorporating counter-measures against fault attacks.

Перейти: https://doi.org/10.1007/978-3-319-44318-8

Дод.точки доступу:
Sklavos, Nicolas. \ed.\; Chaves, Ricardo. \ed.\; Di Natale, Giorgio. \ed.\; Regazzoni, Francesco. \ed.\; SpringerLink (Online service)
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(Асоціація ЕБНІТ)